VLSI

6 subjects · 13 chapters · 52 topics

1. 01

   Digital Design Foundations

   1.1 Number systems and logic

   • Binary, hex and codes
   • Boolean algebra
   • Karnaugh maps
   • Combinational building blocks

   1.2 Sequential logic

   • Latches and flip-flops
   • Counters and registers
   • Finite state machines
   • Timing: setup and hold
2. 02

   HDL and RTL Design

   2.1 Verilog

   • Modules, ports and data types
   • Blocking versus non-blocking
   • Always blocks and sensitivity
   • Writing synthesisable code

   2.2 RTL practice

   • Datapath and control separation
   • FSM coding styles
   • Pipelining
   • Clock domain crossing

   2.3 Verification

   • Testbenches
   • Assertions
   • Code and functional coverage
   • Introduction to SystemVerilog and UVM
3. 03

   The ASIC Flow

   3.1 Front end

   • Specification and microarchitecture
   • Synthesis and constraints
   • Design for test and scan
   • Formal equivalence checking

   3.2 Static timing analysis

   • Timing paths and slack
   • Clock skew and jitter
   • Multicycle and false paths
   • Fixing timing violations
4. 04

   Physical Design

   4.1 Backend flow

   • Floorplanning
   • Placement
   • Clock tree synthesis
   • Routing

   4.2 Signoff

   • Parasitic extraction
   • IR drop and electromigration
   • DRC and LVS
   • Tape-out checklist
5. 05

   Devices and Circuits

   5.1 CMOS fundamentals

   • MOSFET operation
   • CMOS inverter characteristics
   • Power: dynamic, static, short-circuit
   • Logical effort and sizing

   5.2 Memory and low power

   • SRAM and DRAM cells
   • Memory compilers
   • Clock gating and power gating
   • Multi-Vt and voltage islands
6. 06

   FPGA and Project

   6.1 FPGA flow

   • FPGA architecture
   • Synthesis and implementation
   • On-board debugging
   • FPGA versus ASIC trade-offs

   6.2 Project

   • Specifying a digital block
   • RTL and verification
   • Synthesis and timing closure
   • Presenting the results